People Project Prototypes Software Publications

TCC Prototypes
There are currently two prototypes for the TCC architecture:


ATLAS is the first implementation of the TCC architecture. It uses PowerPC 405 processors with a modified data-cache that implements version management and conflict detection for transactional execution. The current design is mapped on a single BEE-2 board, which allows for up to 8 processors. A 9th processor runs Linux and handles system calls and exceptions for the whole system. The design operates at 100MHz and is approximately 100 times faster than our simulation system. It also includes extensive support for debugging and performance tuning. ATLAS is also known as RAMP-Red and is one of the designs in the RAMP initiative.

ProcessorPowerPC 405 (hardcore)
Processor Count8+1
Data Cache32KB, 4-way set associative, 32 KBytes
TM SupportTCC protocol in data cache
OCM BRAM for register checkpoint
InterconnectStar topology
Memory512MB DDR2
SoftwareMontavista Linux 3.1, TCC API



ATLAS: A Chip-Multiprocessor with Transactional Memory Support
Njuguna Njoroge, Jared Casper, Sewook Wee, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun
Proceedings of the Conference on Design Automation and Test in Europe (DATE), Nice, France, April 2007
[Paper PDF] [Talk PDF] [BibTeX]

A Practical FPGA-based Framework for Novel CMP Research
Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, and Kunle Olukotun
© ACM, (2007). This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in the Proceedings of the Fifteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, California, 18-20 February 2007.
[Paper PDF] [Talk PDF] [BibTeX]

Building and Using the ATLAS Transactional Memory System
Njuguna Njoroge, Sewook Wee, Jared Casper, Justin Burdick, Yuriy Teslyar, Christos Kozyrakis, Kunle Olukotun
Workshop on Architecture Research using FPGA Platforms, 12th International Symposium on High-Performance Computer Architecture (HPCA), Austin, Texas, USA, 12 February 2006.
[Paper PDF] [Talk PDF] [BibTeX]


PLUTO is a TCC prototype based on the M32R embedded architecture. M32R is designed by Renesas Technology, which is fully synthesizable core coded by Verilog-HDL and can be programmed to FPGA directly. It provides an efficient platform for supporting architecture development.

PLUTO uses 2 M32R processors each with a modified data caches that implements version management and conflict detection for transactional execution. The two symmetric CPU cores are connected via an internal on chip bus. The bus arbiter supports TCC protocol such as commit, PhaseID controller. The new architecture has Exception/Interrupt for handling TCC overflow and violation.

ProcessorM32R (softmacro core)
Processor Count2
Data Cache8KB, 2-way set associative, 16 Bytes/line
Internal Memory1MB Built-in SRAM (can be replaced with L2)
TM SupportTCC protocol in data cache
InterconnectBus-based shared memory
Memory64MB SDRAM (on board)
SoftwareTCC API, Debian GNU/Linux kernel-2.6 (under porting)


  • Sugako Otani


PLUTO Presentation